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OPEN REQUISITIONSSAN DIEGO AREA July 31, 2008
EXTERNAL CANDIDATES: Please visit our website to complete a profile or to apply for any of these openings: http://jobs.qualcomm.com **QUALCOMM is an Equal Opportunity Employer. **
Business DevelopmentJob Area: Business Development Req #: G1816082 Job Title: Director of Corporate New Business Development Location: California - San Diego Post Date: 7/22/2008 3:02:20 PM Regular/Temp: R # Positions: 1
Education: Engineering graduate degree. . Broad business experience (MBA a plus).
Role: Rewarding and stimulating role within Qualcomm's Corporate New Business Development team. The position will include:
. Study and assess new technologies and markets for Qualcomm. Perform technical and competitive analysis and follow industry/competitive trends. Identify new business opportunities and define required products, solutions, applications, partnerships and licensing agreements.
. Assists the group on technical and system-level issues across a wide variety of projects. Broad engineering/technical experience required. - Provide technical guidance and expertise in system level design and technology architectures to help define prototype / demo developments and trial opportunities. - Supports technical teams in partnering/licensing discussions or in early stage product development of new technologies including developing use cases and requirements.
. Work individually and with cross functional teams (engineering, finance, business/strategy) to develop recommendations, business cases, and development/partnering/licensing plans for new businesses and technologies. Support recommendations with in-depth technical, market, and competitive analysis.
. Establish and manage relationships with third parties interested in partnering, licensing and/or commercializing new technologies with Qualcomm.
Skills: Strong and broad technical system engineering expertise in the areas of wireless communications or consumer electronics with increasing responsibility for detailed technical discussions with partners/customers.
. Solid understanding of business fundamentals and ability to form strategies and influence executive levels.
. Strong communication and relationship building skills. - Able to drive initiatives and coordinate the evaluation of business opportunities with potential customers and partners. - Able to work cross-divisional with different technical teams for the realization of prototypes, demos, trial developments, and handoff for productization.
. Solid background in business development, product management, or technical marketing in wireless communications, wireless networking, or consumer electronics. Successful product introduction track record a plus.
. A motivated, self starter and team player. Capable of multi-tasking and handling conflicting priorities. . Evaluate emerging technologies and proactively distribute findings and formulate potential business strategies: - Ability to concisely brief both technical and business staff on new technologies and corresponding business implications. - Ability to learn about new technologies independently and provide input for the team.
. Entrepreneurial mindset and/or start-up experience a plus.
. Experience relevant to productization of SOCs and ASIC designs a plus.
Job Area: Business Development Req #: N1763150 Job Title: Senior Director Content Licensing Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Business Administration or equivalent experience required. Master's degree in Business Administration or equivalent experience preferred.
Role: This position is responsible for establishing and maintaining MediaFLO's presence and building MediaFLO's relationship with the content community on the west coast and cost effectively securing the license and distribution rights to content for MediaFLO. This position is responsible for managing the relationships and negotiating the licenses for top tier content suppliers. This individual frequently interfaces with senior management and is expected to keep headquarters management aware of developments, reporting on a regular basis.
Manage the day to day relationships with content providers. Negotiate and sign content license agreements, monitor the performance against those agreements, and develop strategies for managing the relationships consistent with the business goals.
Skills: . 10 plus years experience negotiating and licensing programming . 5 plus years licensing digital or new media distribution platforms . 3 to 5 years licensing sports programming . Exceptional negotiation skills . Creative approach to deal structures . Great attention to detail and highly organized . Ability to juggle many complex deals at the same time . Strong financial skills . Relationships for influence in the content business . Strong understanding of the content landscape . Extensive experience in the content licensing business . Experience planning and working within expense and revenue budgets . Manage over 100M in projected license fees . Must work well under deadline pressure . Excellent reading, writing, presentation, and communication skills. . Clear understanding of the MediaFLO aggregator business model . Working knowledge of Microsoft office products. . B.S. degree required, MBA or J.D. preferred
Job Area: Business Development Req #: N1785694 Job Title: Staff Mgr, Business Development - Advanced Technologies Location: California - San Diego Post Date: 7/17/2008 9:17:00 AM Regular/Temp: R # Positions: 1
Education: Master's degree in Business Administration required, Master's degree in Engineering preferred.
Role: This is a hands-on leadership role in driving Advanced Technologies business development efforts. The candidate will work with the management team and engineering in developing, vetting, and presenting product and business concepts to senior management for approvals. Key tasks include: * Drive the idea generating process to identify, conceptualize, and define bleeding edge product and service concepts. * Work with new project proposals to help project teams with business analysis, market research, prototype requirements, business plan development and general business development. * Develop internal and external relationships as required for success of projects, including exploring 3rd-party partnerships to complement internal capabilities. * Coordination with internal groups within the company working on related efforts, including corporate R&D programs and Qualcomm ventures. * University coordination and research liaison
Skills: * Minimum ten years experience with wireless industry, specifically as business development or product manager. * Demonstrated ability to evaluate emerging business opportunities with an integrated view of technical, market, and business factors. * Demonstrated ability to take an idea from conceptual stage to a prototype or product. * Ability to work in a complex, dynamic, technology-based industry. * Solid business analytical skills combined with a good technical background and an interest in emerging technologies. * Self-starter and being self-sufficient are key; must be able to make progress with minimal input and supervision. * Ability to work well in a team. * Accomplish deliverables in an unstructured work environment. * Strong communication skills. * Motivated and a resourceful problem solver.
Engineering - HardwareJob Area: Engineering - Hardware Req #: G1805412 Job Title: Senior Engineer - System Board Level Design Location: California - San Diego Post Date: 7/8/2008 1:07:35 PM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad? suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community. Analysis of Product Requirements and development of architectural specifications
A system board designer is needed for SoC development, evaluation, and reference design boards for wireless connectivity technologies including Bluetooth, WLAN, FM and others.
Responsibilities will include ownership of the entire process from concept to production with sole responsibility for design and checkout. Individual will oversee layout, fabrication, assembly, and manufacturing test.
Skills: At least 5 years of experience with system board design and development involving digital, analog, and RF circuits required. Experience with bench level electrical measurements of RF and analog ICs is required. Experience with FPGA and CPLD designs a plus. Individual must be organized and proficient in documentation. Position requires good communication and interaction with multiple engineering, applications, and operations functions.
Job Area: Engineering - Hardware Req #: G1806274 Job Title: PWB Layout Designer (All levels) Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: Bachelor's, Electrical Engineering required Master's, Electrical Engineering preferred
Role: QUALCOMM CDMA Technologies (QCT) is the world leader in supplying integrated circuit solutions for cellular wireless standards and is the number one fabless semiconductor company in the world. The key to QCT's success is the ability to deliver to our customers complete optimized wireless platforms incorporating protocol, hardware, software and support, with high quality, on schedule. The RF/Analog organization within QCT develops all RF, mixed-signal, and analog ICs for these complete wireless platforms.
In order to drive our next phase of growth in cellular, wireless peripherals and 4G, we are expanding our RF/Analog Product Development and Test Engineering group.
The RF/Analog Product Development and Test Engineering group develops test solutions for design verification of highly integrated RF receivers/transmitters/transceivers, power management, analog and mixed signal ASICs designed by QCT. This group has an opening for a PWB Layout position. Job responsibilities for this position include design, layout, and debug of test interface hardware for both bench top evaluation and high volume ATE production. This would involve route studies, stack-up evaluations, signal integrity analysis and general optimization of complex RF/Analog and Mixed Signal devices.
Skills: . Understanding of electrical engineering concepts, digital and analog circuit design and analysis techniques, sampling theory and DSP fundamentals, communication systems, and RF circuit/matching design (for RF test engineers). . Ability to work with common lab equipment such as oscilloscopes, spectrum analyzers, logic analyzers (for mixed signal), network analyzers (for RF), etc. . Experience with ATE's such as Verigy, Teradyne or LTX. . Knowledge of TSK/Accretech, Electroglas or TEL Probers. . Experienced designing Cantilever, Vertical and Membrane probe designs. . Familiarity with PCB Schematic and Layout tools. ie; Mentor, Cadence, PADS . Exposure to NSP and other fine pitch devices a plus . Hands on experience with board debug a plus. . Ability to communicate clearly, organize effectively, and documentation of work. . Previous applicable work experience with a high tech company is a plus. . ADS, Matlab, Q3D, HFSS, AutoCAD, Sigrity or SI Wave
Job Area: Engineering - Hardware Req #: G1810252 Job Title: Staff Failure Analysis Engineer/Manager Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: BSEE, BSET, or ASEE preferred.
Role: Knowledge of Semiconductor manufacturing process.
Skills: Basic knowledge of Electronic circuits. Knowledge of IC layout navigation software. Knowledge of Semiconductor manufacturing process. Thorough knowledge of physical analysis techniques such as parallel polish, cross-section, and Energy Dispersive X-ray Spectroscopy. Chemical deprocessing, and mechanical sample preparation techniques. Advanced knowledge and experience in operating and maintaining Scanning Electron Microscope equipment. Advanced operating knowledge of Focused Ion Beam systems in order to modify and adjust FIB recipes and processes to be optimized for new process technologies. Install, maintain, upgrade and repair FIB systems and their associated options. Thorough knowledge of Micrion FIB systems, particularly on backside FIB circuit edit tools. Knowledge of Unix and Windows operating systems in addition to C programming language.
Engineering Management experience in a Failure Analysis or Material analysis Lab preferred
Job Area: Engineering - Hardware Req #: G1810755 Job Title: Staff Failure Analysis Engineer/Manager Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: BSEE, BSET, or ASEE preferred.
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry. QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands. QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Skills: Basic knowledge of Electronic circuits. Knowledge of IC layout navigation software. Knowledge of Semiconductor manufacturing process. Thorough knowledge of physical analysis techniques such as parallel polish, cross-section, and Energy Dispersive X-ray Spectroscopy. Chemical deprocessing, and mechanical sample preparation techniques. Advanced knowledge and experience in operating and maintaining Scanning Electron Microscope equipment. Advanced operating knowledge of Focused Ion Beam systems in order to modify and adjust FIB recipes and processes to be optimized for new process technologies. Install, maintain, upgrade and repair FIB systems and their associated options. Thorough knowledge of Micrion FIB systems, particularly on backside FIB circuit edit tools. Knowledge of Unix and Windows operating systems in addition to C programming language.
Engineering Management experience in a Failure Analysis or Material analysis Lab preferred
Job Area: Engineering - Hardware Req #: G1810825 Job Title: Sr. IC Package R&D Engineer Location: California - San Diego Post Date: 7/14/2008 Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Electrical Engineering and/or Materials Science and/or Mechanical Engineering Preferred: Master's, Electrical Engineering and/or Materials Science and/or Mechanical Engineering
Role: This person will work in the package engineering R&D group focused on bring disruptive package technologies into Qualcomm. Their main duties would include; package technology research, interacting with QCT engineering to facilitate design for R&D projects, working with purchasing to create cost models for new technologies, coordinating with suppliers to drive prototyping and testing, write reports on research and experimental results.
The initial focus of this position will be to support the test and failure analysis part of the Embedded Die Substarte project and help to drive this to technology into production. The person will work with SATs and Substrate suppliers as well as the Qualcomm test and FA team to develop new methodologies for testing and analyzing packages with embedded die.
Skills: This person should have 5-10 years of electrical or mechanical engineering background, preferably in the semiconductor packaging. This person should have experience with package testing and/or failure analysis. This person will be highly self motivated with a strong interest in cutting edge technology. They must also have the ability to interact with a diverse group of people from engineering to production. Must have experience in managing international R&D program. Driving program timeline and milestones.
Must be able to create and give presentations to upper management.
Job Area: Engineering - Hardware Req #: E1810977 Job Title: Components Engineer, Staff Location: California - San Diego Post Date: 6/12/2008 11:25:23 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering or equivalent experience required.
Role: Provide Component Engineering support to Design Engineering teams. Provide technical expertise on components, manage information and logistics related to components, and support regulatory objectives.
Skills: Minimum seven years experience in development environment of high tech products. Prefer 10 years experience. Telecommunications experience a plus. Knowledge of WCDMA and CDMA phone level testing preferred. Ability to multi-task and high energy level required.
Job Area: Engineering - Hardware Req #: E1811021 Job Title: Advanced SPICE Modeling/QA Engineer Location: California - San Diego Post Date: 7/12/2008 12:00:04 AM Regular/Temp: R # Positions: 1
Education: Master's or Ph.D. in Electrical Engineering, Physics or equivalent.
Role: The job involves working with the leading semiconductor foundries to develop state-of-the art Low Power CMOS technology to meet Qualcomm's advanced product requirements. As a key member of our process technology team, this engineer will be responsible for advanced 45/32nm and below SPICE model Quality Assurance (QA), model-silicon verification and model releases. The candidate is expected to interact closely with foundry modeling/CAD/device teams and internal design/CAD teams to deliver quality and best-in-class SPICE models for Qualcomm's design communities.
Skills: Good fundamental understanding of device physics related to compact modeling and model-layout-circuit interactions. Minimum of 7 years experience in SPICE modeling/extraction of digital CMOS technology. Familiar with mismatch and Monte Carlos-based simulations. Prior experience in 90nm/65nm model development will be a plus. Expertise in industrial standard SPICE models (BSIM3v3 and BSIMV4) and proficient with next-generation SPICE model development/evaluation (PSP, HiSIM, BSIM5). Experience in setting up rigorous SPICE QA flows, novel benchmarking methodology and customized release flows. Design novel test structure for model-silicon verifications. Hands-on knowledge of commercial EDA design tools (HSPICE, HSIM, Spectra, Cadence Virtuoso, STARRC) and PDK development. Good understanding of how SPICE model interacts with EDA tools. Proficient in developing and using shell scripts for automation and data analysis. Experienced with interfacing with foundries. Good analytical and project management skills. Excellent capability of innovation and creativity. Highly motivated and committed to success of the individual and the team. Superior interpersonal communication skills. Publish technical reports. Able to work flexible hours. Occasional domestic/international travels needed.
Job Area: Engineering - Hardware Req #: E1811080 Job Title: Advanced SRAM/ROM Memory Technology Development Engineer Location: California - San Diego Post Date: 7/13/2008 12:00:05 AM Regular/Temp: R # Positions: 1
Education: Master's or Ph.D degree in Electrical Engineering or related field.
Role: Being part of the process technology team in the largest fables design house, you will be responsible for the process development of embedded memory solution (SRAM, ROM and fuse) in 32nm CMOS platform technology. This role requires interfacing with foundry process team and internal design teams. Good communication skills are highly desirable. Job responsibilities include memory technology spec definition (cell size, leakage, performance, etc), bitcell design and characterization, manage foundry bitcell & model delivery, drive SRAM yield and Vccmin improvement and develop advanced bitcell solutions to meet performance, power target. Candidate will also be responsible for the reliability of the memory technology such as SER and NBTI, etc.
Skills: This challenging role requires candidate to have 7+ year experience in process and device development. Experience in embedded memory development at advanced technology node, such as 45nm or 32nm SRAM, is highly desired. Candidate must have solid understanding of device physics, process integration, bitcell design, SRAM failure analysis and strong data analysis skills. Candidate should be able to perform in depth analysis on cell read and write margin. Candidate should also have basic understanding of SRAM design and SPICE model simulation. Candidate should have good verbal and written communication skills and project management skill. Experience with Monte Carlo simulation and Cadence tools is a plus. Experience in DRAM, Flash and other memory technology is also a plus.
Job Area: Engineering - Hardware Req #: G1811433 Job Title: Systems Engineer, Sr.-USB Location: California - San Diego Post Date: 7/14/2008 1:16:14 PM Regular/Temp: R # Positions: 1
Education: BSEE required, MSEE preferred
Role: As a USB Systems Engineer, you will be responsible for: Link, PHY, and Hardware system design Integration of High Speed USB cores (multiple, with multiple configurations) into various targets: MSM, MDM, QSD, QST SURF and FFA development guidelines Running in a mobile environment Address clock regime Address power regime Standby mode/TCXO shutdown/Sleep mode/Power collapse mode Low power mode operation Standard (USB-IF) for both 2.0 and 3.0 Interaction with AirGo to address their USB needs Working with all engineering teams and with marketing Establish hardware road map and release plan Travel both domestic and international
Skills: Experience in the system definition, functional partitioning, performance analysis, troubleshooting and support of high-speed USB interfaces used in Qualcomm's current and next generation ASICs. Experience with USB 2.0 compliance testing, link protocol, physical signaling, power management, link performance, driver optimization, EHCI, debug with USB bus/protocol analyzers, logic analyzers and/or oscilloscopes. C and assembly language programming, knowledge of SOC design including ARM, AMBA, verilog/VHDL, verification, synthesis, physical design, circuit board design, and/or signal integrity are desired. A minimum of 3 years direct experience in USB design and verification are required.
Job Area: Engineering - Hardware Req #: E1812388 Job Title: Engineering Technician - Engineering Technician, Senior Location: California - San Diego Post Date: 6/18/2008 11:05:39 AM Regular/Temp: R # Positions: 1
Education: Requires a two-year technical degree, trade school, or related military experience. A background of education including: basic math, physics, scientific and engineering notations, trigonometric functions, algebraic studies in factoring, exponents, logarithms and manipulation of equations is essential.
Role: Assist Engineers in areas such as HW testing, verification, modification, bread-boarding, and assembly of prototype electro-mechanical systems. Applications may include some digital and analog circuits. Must be able to work independently and take on directions from various project leads. Two years of experience in an R&D environment desired.
Skills: Proficient in Digital circuit and system testing/debug. Able to work from schematics, diagrams, written and verbal descriptions to perform testing or isolating fault at either a board or a system level. Know how to operate test equipment (i.e., oscilloscope, logic analyzer, digital multi-meter, spectrum analyzer, etc). Possess excellent written and verbal communication skills. Working knowledge of basic Antennas, RF circuits, and networking concepts are a plus.
Job Area: Engineering - Hardware Req #: G1813138 Job Title: MRAM Test and Characterization Engineer Location: California - San Diego Post Date: 6/5/2008 3:17:24 PM Regular/Temp: R # Positions: 1
Education: Master's in Electrical Engineering plus 5 years of test experience
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of wireless chipset and software technology and the number 1 fabless semiconductor company in the world. Our integrated chipset solutions offer handheld device manufacturers reduced bill-of-materials costs, time-to-market, and feature rich solutions. Mobile handheld devices powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands. QCT values collaboration with its partners and works closely on new product and technology development.
A Test and Characterization Engineer would work with fab, process technology and design teams to develop test and automation methodologies. Candidate would work with and develop internal tools for test vectors and test program generation, vector tracking, test program release, etc. In addition, candidate would also work on include design and debug of test interface HW, test SW development, HW/SW integration, characterization test, releasing cost effective production test solutions into mass production, and test time reduction activities.
Skills: Knowledge of Linux and UNIX Experience with programming in Perl, C/C++. and Java Knowledge of semiconductor manufacturing process Understanding of design for test, design for debug, digital/analog test methodologies and circuit analysis skills Hands on experience with Automated Test Equipment (ATE) such as Verigy 93K and/or memory testers Test program development, datalog analysis and reporting Experience with Production Test Minimum of 3 years in memory manufacturing experience Minimum of 2 years in 300mm CMOS silicon technologies, preferably with embedded memory density products such as SRAM and eDRAM or eFLASH Vector Translation, DFT Experience Desirable. SQL, Excel Marco Experience Desirable
Job Area: Engineering - Hardware Req #: G1813561 Job Title: TSV Memory Interface Controller Design - Senior Logic Designer Location: California - San Diego Post Date: 7/18/2008 9:29:40 AM Regular/Temp: R # Positions: 1
Education: Master's Degree in Electrical Engineering required
Role: Seeking experienced Digital Design Engineers for San Diego site to work on commercialization of Through-Silicon-Via (TSV) technology. Low power micro-architecture design techniques, high quality and low cost are all key design points for our products. Elegance and efficient verification experienced are also valued. Leading edge process technologies such as 65nm and 45nm are in design with 65nm products already in production.
The candidate will be expected to work with a small team of engineers working on commercializing Through-Silicon-Via technology. Tasks such as configuration of memory controller IP cores, design of interface logic, timing constraint development, synthesis support, floorplanning of block and IO support, and verification at the unit and SOC level are all areas of execution that the candidate will be expected to contribute too. The candidate will also have opportunities to help with Silicon level planning, bringup, and verification of functionality.
Skills: Experience in the development and integration of AHB/AXI bus components, DRAM memory controllers, Cache Architectures and Cache controller designs into SOC designs. A list of these technologies include: SDRAM, LPDDR, DDR2, DDR3, NAND and other commercially available memories. Experience with some or all of these is required.
Knowledge of ASIC design including architecture, verification of integrated system, RTL, synthesis, and timing closure. Specific experience with Synopsys DC/PC, Vera, Spyglass, PTSI, Blast, Verilog and VHDL tools/languages are all pluses.
A minimum of 5 years product design experience. C programming, ARM architecture, Lab test equipment, Signal integrity.
Job Area: Engineering - Hardware Req #: E1813578 Job Title: RF Applications Engineer, Staff Location: California - San Diego Post Date: 7/24/2008 11:22:01 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering preferred.
Role: The successful candidate will become a key member in QCAE (Qualcomm's Computer Aided Engineering Group), responsible for providing training, design services, design automation, and methodology support for Qualcomm's RF, Signal Integrity, and System engineers.
Skills: RF Hardware Engineer with 3 years minimum experience in designing low level RF circuits including CDMA Receiver and Transmitter chains. Must have experience with RF layout techniques on multi-layered board materials. Candidate must obtain strong technical writing skills, be able to present engineering materials clearly, and be able to interact well with other engineers.
Candidate must have basic knowledge of Electro-magnetics and RF theory (S parameters, matching, noise figure, stability, etc.).
Candidate should have experience using various RF simulation software such as ADS, MWO, VSS, HFSS, Q3D, TPA, Microstripes, IE3D, Hspice, Pspice, SI Wave, Sigrity, Eagleware, Polar, or Hyperlynx.
Experience using Matlab, the Unix System, programming languages such as Java, C, perl, or tcl is a plus. Education Requirements: Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering or equivalent experience preferred.
Job Area: Engineering - Hardware Req #: E1813896 Job Title: Director of Product Engineering Location: California - San Diego Post Date: 7/2/2008 9:32:33 AM Regular/Temp: R # Positions: 1
Education: Minimum Bachelor's degree in Engineering.. Master's degree in Engineering is a plus. Formal leadership and business management training is desired.
Role: QUALCOMM MEMS Technologies Inc.(QMT) designs and manufactures mirasolTM display products based upon an advanced MEMS (Micro-Electro-Mechanical-Systems) technology. mirasolTM display modules combine superior readability over a wide range of ambient conditions with significantly lower power consumption than conventional displays, making them ideal for a broad range of portable and battery-powered applications.
The Product Engineering organization within QMT is responsible for design, development, and delivery of mirasolTM display modules, including management of the entire product lifecycle, definition and maintenance of project specifications, schedules and deliverables, and maintenance of the technical customer interface (in coordination with Sales and Applications Engineering).
The Director of Product Engineering leads QMT's Product Engineering organization including responsibility for project engineering, program management, module design, and module component development. Besides managing engineering and program resources to accomplish QMT's business goals, the Director of Product Engineering provides input into QMT's R&D organization to insure targeted technology planning. This individual is also the primary engineering interface to Strategic Sourcing and Supplier Management for module component sourcing.
Skills: The successful candidate will possess significant depth in the leadership of multi-disciplinary teams, managing and executing hardware integration, providing technical leadership of complex product development, managing risk, and completing projects on time and to performance specifications. This individual must have demonstrated expertise in project planning for the product lifecycle combined with excellent communication skills to convey product and component status to a broad audience. Additionally, the successful candidate will have- . Experience in display device product development and manufacturing . A track record of consumer device deployment successes (from concept through to high volume commercial shipment) . Experience building an engineering team; staffing and mentoring . Experience managing electronic manufacturing services (EMS) . Experience exploiting existing technologies in partnership with component suppliers . Proven problem-solving skills, strategies and tactics, used in a variety of project areas. . Excellent analytical capabilities and decision-making skills in the presence of ambiguity and conflicting information. . Excellent interpersonal, organizational, negotiation and written and verbal communication skills. . Ability to understand organizational and team dynamics in order to provide appropriate direction for team activities and the resolution of complex issues. . Some local and international travel is required.
Job Area: Engineering - Hardware Req #: G1814281 Job Title: ASIC Test Engineer - Test Engineer/Sr. Test Engineer Location: California - San Diego Post Date: 6/17/2008 10:53:11 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering preferred.
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
ATE Mixed Signal & High Speed Digital Test for characterization and production test. Verigy 93k experience is preferred. RF Test experience is a plus.
Skills: - Three to five Years ATE Experience Desirable: Digital, High Speed Digital Interfaces, and Mixed Signal; or RF, or Power Management IC Experience. - Verigy 93K experience preferred. - Knowledge of Production test and characterization on ATE. - Vector Translation - Loadboard Design
Job Area: Engineering - Hardware Req #: E1814873 Job Title: Digital ASIC/FPGA Engineer - (NoC Study) - Corporate R&D Location: California - San Diego Post Date: 7/31/2008 10:21:01 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering preferred.
Role: QUALCOMM Corp R&D has a mission to advance core CDMA and OFDMA and other advanced wireless communication technologies. Key innovations in CDMA such as 1x EV-DO were conceived and brought to market by corporate R&D. Leading edge research and implementation of new technologies and methods are also a key focus.
This position is for an ASIC/FPGA engineer who can apply network theory to implement efficient hardware designs for packet routers, switches and on-chip networks to address quality of service and network performance requirements. The work includes research studies, architecture design, hardware definition and design, network modeling, test and integration.
Skills: Opportunities exist for an exceptional ASIC/FPGA designer who will design and develop complex digital ICs. Requires solid knowledge of network and information theory, digital logic design, timing, electrical analysis, and good working knowledge of Verilog or VHDL. Design experience in FPGA or IC development within a UNIX environment, good working knowledge of C/C++ scripting, and VHDL for simulation and synthesis is preferred. Must have excellent interpersonal and teamwork skills, and proven ability to work effectively in a fast-paced environment.
Job Area: Engineering - Hardware Req #: E1815284 Job Title: 3D Technology Integration Engineer Location: California - San Diego Post Date: 7/28/2008 12:05:50 PM Regular/Temp: R # Positions: 1
Education: Masters or Doctorate degree in Electrical/Chemical Engineering or Physical/Material science required.
Role: The candidate will be responsible for the development and qualification of 3D chip stacking process technology by working with external partners (foundry, SATS and consortia), product, system architect, packaging, design and technology teams. The candidate will also be active in generating IP. The tasks include:
Define the physical and electrical design rules for 3D chip stacking based on the trade off of product requirements and supplier capability. Define process module incoming and outgoing requirements for all 3D modules. Working with technology team and suppliers to define optimal 3D chip flow. Run DOE with suppliers to optimize the process margin and ensure a robust process integration. Work with suppliers on process development and qualification. Drive suppliers to deliver the process modules meeting the requirements and meet test chip and product timeline. Develop methodology to ensure smooth process transition between multiple suppliers. Design structures and methodology to detect 3D stacking induced impact to devices and circuits, optimize the process with suppliers to minimize the impact.
Skills: Work with reliability engineering team to ensure high integrity and reliability for 3D chip stacking Knowledge of CMOS devices, and advanced node (65 and 45 nm) technology. 3+ years CMOS process integration in particular on BEOL. Experience of setting design rules, robust process integration, and process development and qualification Knowledge of IC package process and technology would be a plus. Knowledge of 3D chip stacking technology, knowledge 3D process stacking module (through Si via, thinning and bonding) would be a plus. Experience of working with cross function teams: foundry, SATS, product, design and test, experience of lead a team to delivery positive results. Experience or knowledge of CMOS device or package reliability characterization Knowledge of 3D technology application and experience on test chip design
Job Area: Engineering - Hardware Req #: G1816778 Job Title: I/O Engineer Location: California - San Diego Post Date: 7/23/2008 10:25:05 AM Regular/Temp: R # Positions: 1
Education: MS in Electrical Engineering required. PHD in Electrical Engineering preferred.
Role: Work with existing design team to architect, design, layout and characterize high performance low power off-chip receivers & drivers. Work with test team on characterization/testing of high speed IOs.
Skills: Knowledge of DDR, LVDS, SSTL & SerDes. In depth knowledge of full custom layout and experience working closely with mask designers. Extensive knowledge and experience in the use of SPICE simulators, preferably HSPICE. Ability to use schematic capture tools and in depth understanding of SPICE netlisting. Prefer knowledge of Cadence Analog Artist & Virtuoso Ability to write shell scripts (PERL preferred) to automate circuit design tasks and for general text parsing/manipulation. Ability to efficiently work on multiple projects simultaneously, including management of multiple derivative products from an existing base design.
Job Area: Engineering - Hardware Req #: G1816893 Job Title: Design Verification Engineer (ASIC, Vera, C++) - Corp R&D Location: California - San Diego Post Date: 7/21/2008 11:45:34 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering
Role: Hardware Verification - ASIC Vera C++ / Verification Engineer
Experienced chip verification engineer responsible for designing and developing verification environment components, and writing, executing and debugging tests from testplans or functional specifications. Will work directly with various project teams to assist with the deployment of design for verification methodologies. Verification components to be developed may include bus functional models/transactors/bus interface models, data/transaction and scenario generators, bus monitors, checkers, and coverage models.
Skills: Hardware Verification Engineer - Senior ASIC Verification
Qualifying hardware engineering candidates must possess in-depth knowledge of design for verification methodologies. They are expected to be able to articulate how to apply such techniques as assertions, directed random test generation and coverage to full chip verification. ASIC verification experience should include use of modern verification techniques, tools, and languages. Must be skilled in Vera (or Specman E / Specman-E), C++/OOP, and have a strong background in data structures and algorithms. ASIC Design experience using industry-standard hardware description languages (Verilog/VHDL) is highly desirable.
Excellent verbal and written presentation/communication skills are mandatory. Strong interest and understanding of design for verification methodologies is required. Must have excellent interpersonal and teamwork skills, strong problem solving skills, and a proven ability to work effectively in a fast-paced environment.
5+ years of hands-on ASIC verification experience is required. Experience with scripting languages, preferably Tcl and perl. The candidate must be familiar with the software development process and related tools on Unix/Linux platforms.
Job Area: Engineering - Hardware Req #: G1649008 Job Title: ASIC Design/Modem Architect Location: California - San Diego Post Date: 7/8/2008 9:29:38 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering or equivalent experience
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
Qualcomm CDMA Technologies is looking for several creative engineers (at all levels) to develop next generation wireless modems (CDMA, UMTS, OFDM, GSM, and etc). Responsible for system architecture definition, and/or RTL implementation.
Skills: Solid understanding of Discrete-time Signal Processing and Digital Communications.
Knowledge of ASIC design including architecture and/or RTL design.
Job Area: Engineering - Hardware Req #: E1791952 Job Title: Senior RF Engineer Location: California - San Diego Post Date: 7/16/2008 4:42:43 PM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering required.
Role: Working with The Office of the Chief Scientists of Qualcomm to research and develop innovative wireless devices with the latest QUALCOMM MSMs (Mobile Station Modems), RadioOne RFICs, MFLO ICs and Power Management ICs for smart phones and multimedia handsets. Provide radio design including RF system analysis, link budget, RX/TX architecture, filter requirements/design, detailed hardware design, PCB layout supervision, and component selection. Applicant can expect to support a range of project requirements, R&D programs, and work in a multi-discipline environment.
Skills: Experience in the design, development, and testing of cellular phones using QUALCOMM chipsets is required. Candidates should also understand the design of LNAs, receivers, transmitters, power amplifiers, power control loops, and PCB layout for consumer wireless systems up to 3GHz. Knowledge of the physical layer of CDMA, wireless LAN/WAN, GPS, and Bluetooth desired. Understanding of digital communications and interfacing with digital hardware desired. Must have good verbal and written communication skills.
Job Area: Engineering - Hardware Req #: G1792212 Job Title: SOC Architect Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: BSEE required, MSEE preferred
Role: The SOC architecture group consists of a multi-disciplinary group involved in early product specification and analysis effort. The successful candidate will play a key role in driving many of the early architectural decisions related to a product family.
In addition, the candidate will be exploring tools and methodologies to identify new opportunities and frameworks for architectural exploration throughout the life cycle of a product. Close collaboration with the Systems, Software and ASIC development groups to understand and assess requirements and come up with models and techniques. Continue throughout the product cycle to monitor and validate system models and calibrate them.
Qualifying candidates will participate and lead tool, process and methodology related evaluations, analyze results and make recommendations to the various development groups. The candidate has to be hands on, detail oriented and technology savvy, to recognize synergies between different systems and methodologies. This is a high level, high exposure position, having a direct impact on early product planning phase, through performance and cost analysis.
Skills: A minimum of 10 years of experience in systems, software of ASIC design and development, with a proven track record of multiple tape outs. Strong working knowledge of modeling tools and techniques. Strong working knowledge of architecture tradeoff analysis and modeling tools, commercial and in-house (C/C++, systemC, MATLAB). Strong exposure to micro-architecture analysis and implementation. Strong exposure to bus performance analysis and design tradeoffs. Exposure to SW development practices. Exposure to HDL development flows and processes. Exposure to HW acceleration and emulation platforms. Exposure to algorithm analysis, evaluation and development techniques. Familiarity with architecture tradeoff analysis and modeling tools, commercial and in-house (C/C++, systemC, MATLAB). Familiarity with ESL tools and flows. Familiarity with Best of Class industry wide practices. Exposure to various architectures (telecom and multi-media), bus protocols (AMBA, CoreConnect, OCP) Familiarity with scripting languages: perl, tcl, shell, etc. Familiarity with code generation tools: yacc, bison, etc
Job Area: Engineering - Hardware Req #: G1794612 Job Title: Emulation/FPGA Engineer Location: California - San Diego Post Date: 7/29/2008 1:56:58 PM Regular/Temp: R # Positions: 1
Education: Bachelor's Degree in Electrical Engineering required, Master's Degree in Electrical Engineering preferred.
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
As part of the Emulation Team, you will: Port ASIC RTL code to FPGA environment. Work on the synthesis and Place And Route (PAR) the RTL code to custom / off the shelf emulation platforms. Write various constrain files and perform speed optimization Work in the lab to debug FPGA builds and perform bring up tasks Collaborate with ASIC hardware designers to resolve RTL issues Work with software, AST, and VI (Verification / integration) team in resolving VI / FPGA issues Work on the Partition of the ASIC RTL code across the custom emulation hardware platforms Create emulation plans for various MSM projects. Design new custom emulation hardware platforms. Contribute to the board design activities. Lead emulation activities for MSM projects and collect requirements from various customers of the emulation activities. Work on various emulation specific design activities.
Skills: Minimum experience of 2 full years working closely with large FPGAs. Requires a strong digital foundation in design (VHDL), simulation, synthesis (DC), place/route, integration, and debug. Qualifying candidates should be able to quickly assimilate and refine existing designs; apply test equipment and problem solving skills in the lab; maintain designs under revision control; and actively contribute toward the validation of QCT ASICs using FPGA emulators. Must be a self-starter and team player with a solid understanding of electrical engineering fundamentals. High-speed digital board design and/or knowledge of chip verification very desirable. Mobile phone, Microprocessor, ASIC, or gate array experience beneficial.
Job Area: Engineering - Hardware Req #: G1717596 Job Title: Verification/Integration Engineer Location: California - San Diego Post Date: 7/13/2008 12:00:05 AM Regular/Temp: R # Positions: 2
Education: Bachelor's Degree in Electrical Engineering; Master's Degree in Electrical Engineering or PhD preferred.
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Design, Code and Test real-time embedded software to perform verification tasks for IS-95, GSM, HDR, and WCDMA MSM chip-sets in a phone target platform. The tasks include developing software to perform device level and system level verification and validation.
Skills: Strong background in real-time embedded software development. Have working knowledge of real-time operating system. Efficient in C programming. Knowledge of any wireless standard (IS-95, GSM, HDR, and WCDMA) Physical layers processing and call processing is a plus. Strong background in system integration and troubleshooting skills. Real-time embedded C programming and a good understanding of IS-95 system. Microprocessor design/debug experience (low-level) - capable of performing timing analysis, designing hardware for experiments, etc. Diagnostic equipment familiarity: ICE, Logic Analyzer,... Familiarity with VLSI design and design-flow & VHDL. Familiarity with board-level layout Experience on PC and UNIX platforms High initiative - we are often doing things not done previously. Hands-on lab debugging & troubleshooting skills
Job Area: Engineering - Hardware Req #: G1670810 Job Title: Bench Test Engineer - Mixed Signal Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
Role: Entry level Engineer to all levels of Sr Engineer(ie. Sr, Staff, Sr Staff, Principal)
QUALCOMM CDMA Technologies (QCT) is the world leader in supplying integrated circuit solutions for cellular wireless standards and is the number one fabless semiconductor company in the world. The key to QCT's success is the ability to deliver to our customers complete optimized wireless platforms incorporating protocol, hardware, software and support, with high quality, on schedule. The RF/Analog organization within QCT develops all RF, mixed-signal, and analog ICs for these complete wireless platforms.
In order to drive our next phase of growth in cellular, wireless peripherals and 4G, we are expanding our RF/Analog Product Development and Test Engineering group.
The RF/Analog Product Development and Test Engineering group develops test solutions for design verification of highly integrated RF receivers/transmitters/transceivers, power management, analog and mixed signal ASICs designed by QCT. This group has an opening for a Mixed Signal Bench Test Engineer position. Job responsibilities for this position include design and debug of test interface hardware, test methodology implementation, test equipment automation, and device verification/characterization.
Skills: Understanding of electrical engineering concepts and circuit solving skills Working knowledge of ADC, DAC, and general communication measurements (ie INL, DNL, Gain and Offset Error, SFDR, THD+N, ICN, etc) Able to work with common test equipment (oscilloscope, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, etc) Capable of understanding and modifying LabVIEW test software Knowledge in mixed-signal or analog PCB design including CAD interface Test board design, debug, and development Ability to communicate clearly, organize effectively and document work thoroughly Familiarity with cellular standards such as CDMA2000, 1X-EVDO, WCDMA, UMTS, GSM/GPRS/EDGE, or wireless peripheral standards such as 802.11x WLAN or other OFDM-based systems, GPS, and Bluetooth is desirable.
Job Area: Engineering - Hardware Req #: G1729069 Job Title: Probe Card Development Engineer (All levels) Location: California - San Diego Post Date: 6/20/2008 11:05:57 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
Coursework to include: Digital and Analog circuit design RF fundamentals DSP fundamentals C and/or Visual Basic programming Engineering Labs Semiconductor Physics
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
The RF/Analog IC Product Development group has an opening for a Probe Design Engineer. This group develops test solutions for design verification and high volume production testing of Zero-IF (ZIF) RF receivers/transmitters/transceivers, baseband mixed-signal receivers, audio devices, and power management ASICs.
Skills: . Understanding of electrical engineering concepts, digital and analog circuit design and analysis techniques, sampling theory and DSP fundamentals, C, LabView and/or Visual Basic programming, communication systems, and RF circuit/matching design (for RF test engineers). . Ability to work with common lab equipment such as oscilloscopes, spectrum analyzers, logic analyzers (for mixed signal), network analyzers (for RF), etc. . Experience with ATE's such as Verigy, Teradyne or LTX. . Knowledge of TSK/Accretech, Electroglas or TEL Probers. . Experienced designing Cantilever, Vertical and Membrane probe designs. . Familiarity with PCB Schematic and Layout tools. ie; Mentor, Cadence, PADS . Hands on experience with board debug a plus. . Ability to communicate clearly, organize effectively, and documentation of work. . Previous applicable work experience with a high tech company is a plus. . ADS, Matlab, Q3D, HFSS, AutoCAD . Sigrity or SI Wave
Job Area: Engineering - Hardware Req #: G1732909 Job Title: Hardware Engineer - Board Level Digital Hardware Design (Multiple Levels-Positions) Location: California - San Diego Post Date: 6/16/2008 12:11:31 PM Regular/Temp: R # Positions: 5
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience
Role: Develop CDMA phones with the latest QUALCOMM MSMs (Mobile Station Modems), RadioOne RF ICs, and power management devices for smart phone and multimedia applications. Design, analyze, integrate, verify, and maintain digital hardware and circuit card assemblies. You will design platforms that include ultra high performance ARM processor, integrated 3D graphics, streaming video, digital signal processing, ultra-low power consumption, CD quality audio, USB OTG, Bluetooth, GPS, and 802.11.
Responsibilities include board-level digital, power, analog design, analysis, and test. Design and simulate state of the art high density PWB/PCBs. Must be able to quickly assimilate and refine existing phone hardware designs; apply integration and problem solving skills in the lab; read and write specifications and requirements, work closely with software and RF engineers, and actively contribute toward the evolution of our products.
Skills: Multiple positions offered at various levels. Seeking 3-12 years experience. Ideal candidate should have experience in consumer electronics, wireless, or low power design.
Solid understanding of electrical engineering and circuit fundamentals. Strong knowledge of both digital and analog design. Baseband hardware and circuit card design, including digital, analog, and audio. Strong lab skills a plus. Knowledge of transmission lines, cross talk, efficient low-power supply design, decoupling, and layout of high performance digital circuits. FPGA and CPLD design experience. Familiarity with modems, DSPs, microprocessors, memories, LCD's, batteries, voltage regulators, camera sensors, and other consumer electronics hardware. Embedded programming skills. Excellent interpersonal and teamwork skills. Outstanding communications skills, oral and written. Project leadership. Assertive go-getter who gets things done.
Job Area: Engineering - Hardware Req #: G1682469 Job Title: Foundry Engineer Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: Bachelor's Degree in Electrical Engineering & advanced degree preferred
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad? suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Senior level position to drive foundry and process related issues for current and next generation technologies. Position may be defined as working with one or more foundries on development technologies and/or production technologies. Work with QCT teams (Design, SOC, PTE) to identify support required from foundry. Identify design enablement & schedules needed to support product roadmap. Provide primary interface to foundry to communicate QCT requirements. Co-ordinate day-to-day, near term and longer term technical projects between QCT and foundry for timely closure. Co-ordinate as-needed, weekly and periodic technical meetings with foundry. Co-ordinate release of test chips and products with hand-off requirements identified and completed with foundry. Resolve on-going device related issues for yield, reliability, performance, delivery with foundry in co-ordination with PTE team. Engage with foundry in support of advanced technology development for future technologies for QCT roadmap. Position will require fairly frequent travel domestically & oversees
Skills: 6+ years of semiconductor industry experience with a minimum of 3 years working directly with foundries such as TSMC, IBM.
?Thorough understanding of device physics, reliability concepts and CMOS wafer processing at deep submicron nodes.
?In depth understanding of ASIC design flow & methods including design & verification tools.
?Knowledge of circuit design techniques for ASIC libraries, memories, i/o etc.
?In depth knowledge of ASIC supply chain including wafer supply, mask making, wafer prep, test & packaging functions
?Excellent communications skills verbal & written A plus to have 2nd language (Korean) skills w/ Asian suppliers
Job Area: Engineering - Hardware Req #: G1609328 Job Title: Multimedia ASIC Design Engineer Location: California - San Diego Post Date: 7/20/2008 12:00:01 AM Regular/Temp: R # Positions: 1
Education: BS/MSEE with 5+ years of related experience.
Role: Position will be responsible for the design, verification and implementation of hardware blocks in the area of 3D and 2D graphics, video compression/decompression, TV and LCD display, audio and cameras. Past experience designing blocks in these areas is a big plus.
Skills: The candidate should have previous experience in designing cores and ASICs for production. This experience should include knowledge of VHDL or Verilog, Synopsys tools, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT). Specific experience in the design and verification of multimedia-related blocks is desirable. Knowledge of digital signal processing and/or computer arithmetic, as well as past experience with CPU/DSP architectures also desired.
Job Area: Engineering - Hardware Req #: G1609329 Job Title: ASIC - Digital Design Engineers Location: California - San Diego Post Date: 7/29/2008 10:50:01 AM Regular/Temp: R # Positions: 4
Education: Master's Degree in Electrical Engineering preferred
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
The MSM and CSM design group in QCT is seeking experienced Digital Design Engineers for its San Diego site. The work will expose the designer to a large number of wireless standards, including: 1x CDMA, UMTS, GSM, GPRS, EDGE, 802.11, BT, OFDM, UWB, and others. Additionally, many of our products integrate exciting multi media features, such as H.263, H.264, MPEG, 2D/3D graphics, TV encoding technologies, and digital camera technologies. Low power micro-architecture design techniques are key design point features of these chips. Elegance and efficient verification are valued design techniques. High quality and low cost are all key design points for our products. Leading edge process technologies such as 65nm and 45nm are in design with 65nm products already in production.
Skills: Knowledge of ASIC design including architecture, verification of integrated system, RTL design, synthesis, and timing closure. Specific experience with DC/PC, Vera, LINT, PTSI, and VHDL are all pluses. Experience with complex SOC integrations, including advanced verification techniques are a must. Design experience and background in low power, high volume applications are desired.
Job Area: Engineering - Hardware Req #: G1799312 Job Title: Layout Parasitic Extraction Engineer Location: California - San Diego Post Date: 7/2/2008 9:16:42 AM Regular/Temp: R # Positions: 1
Education: Requires MSEE and 5 years experience or higher degree
Role: Develop and support solutions for parasitic extraction of VLSI designs for timing, power-grid and signal integrity analysis. In this role you will support extraction of ASIC, custom digital, analog and RF designs. Perform development and validation of extraction rule files for industry standard extraction tools. Provide extraction support for both full chip and block designers and develop infrastructures to automate the extraction steps.
Skills: - 4 or 5 years hands-on experience with parasitic extraction tools. - Experience in run set development with Synopsys Star-RCXT, Mentor Graphics &n |
